Vector Graphic

Front of the unit, Front again showing internals, Top-down overview, closeup of the card cage slots, a 64k Memory board, FlashWriter II, BitStreamer II.

Disk drive and Power Supply, Hard drive cabinet, closeup of the hard disk.

Linked here you will find three pictures of Jonas and I debugging it to work out why it isn't doing, well, anything. Logic analysers rock!
Picture one
Picture two
Picture three

Several weeks later I caved and bought my own logic analyser, an HP 1631G, with seven pods of data logging goodness. Talk about magic! Here's my first attempt, ever, of running the system solo.
First we see the initial setup of three of the state pods stacked together. I'm running the tracer from a single CLK line on one of the pods, which is connected to the MEMRQ pin on the Z80. I then have the entire data bus (8 bits) and address bus (16 bits) connected. Lastly I am going to trigger off the RESET line, so I know when to start capturing data from the system.

Next, we a close up of the processor with all the grabbers on it. Boy these things are fiddly.

Now as good a picture as I could take of the Analyser in trace-setup mode. I'm telling it to start capturing when RESET goes to 1 (as the Z80 resets when RESET is pulled low).

Finally here we have the trace after the Vector is powered up. You can see the first op executed is a JMP (0xC3) to 0xE028 which is from the vector table up into the ROM monitor. (The first column is the logic analyser's internal state counter, next is the value of the RESET line (high), next what is on the data bus, and then what the address bus is currently set to.